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9.3
Reset Timing (Inactive Clock Polarity Low Shown)
CS
SCK
RESET
SO
SI
HIGH IMPEDANCE
tREC
tRST
tCSS
HIGH IMPEDANCE
Note:
9.4
The CS signal should be in the high state before the RESET signal is deasserted.
Command Sequence for Read/Write Operations (except Status Register Read)
SI
CMD
8 bits
8 bits
8 bits
MSB
r r r r rXXX
XXXX XXXX
XXXX XXXX
LSB
Reserved for
larger densities
Page Address
(PA9-PA0)
Byte/Buffer Address
(BA8-BA0/BFA8-BFA0)
Notes:
16
1. “r” designates bits reserved for larger densities.
2. It is recommended that “r” be a logical “0” for densities of 2M bits or smaller.
3. For densities larger than 2M bits, the “r” bits become the most significant Page Address bit for the appropriate density.
AT45DB021B
1937J–DFLSH–9/05
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